The present invention relates to a phase control technique, and a semiconductor device and a semiconductor memory activated in synchronism with a clock signal, and particularly to a phase control technique capable of controlling the phase of an internal clock signal synchronized with an externally-input clock signal so as to match an external output operation with the phase of the external clock signal. The present invention relates to a technique effective for application to a clock synchronous memory like an SDRAM (Synchronous Dynamic Random Access Memory), for example.
An SDRAM performs the input/output of data in synchronism with a clock signal inputted from the outside. When the operating frequency of the SDRAM is improved or made upward to shorten a clock cycle time, an access time required to read data according to its clock cycle must be shortened. Therefore, a phase control circuit or a clock reproducing circuit for reducing a clock skew between the external clock signal and an internal clock signal for data output control regardless of the frequency of the external clock signal, in other words, constantly matching the phase of the external clock signal with that of the internal clock signal for data output control has been adopted.
As conventional clock reproducing circuits, there are known those using PLL (Phase Locked Loop) and DLL (Delay Locked Loop). Since, however, they are feedback circuits, even a few hundred cycles are required to match the phase with a predetermined one, time is required to return them from a standby state to an operable state. Further, they must be always activated even during standby in order to avoid it, so that stand-by power increases.
Therefore, SMD (Synchronous Mirror Delay) has been proposed in International Solid-State Circuit Conference Digest of Technical Papers, pp. 374-375, February 1996 as a clock reproducing circuit capable of stopping its operation on standby. The SMD has a series of two delay circuits, i.e., a traveling-direction or forward delay circuit, a reverse or backward delay circuit, a mirror image control circuit and a delay monitor. The forward delay circuit and the backward delay circuit are placed in such a manner that signal transfer paths are opposite to each other. The outputs of respective delay stages of the forward delay circuit are respectively connected to the inputs of their corresponding delay stages of the backward delay circuit through the mirror image control circuit. The delay monitor is a dummy circuit for a delay time of a clock input buffer and a delay time of a clock driver. The operation of the SMD will be described in the above-described reference as will be described below. An nth clock first passes through the delay monitor and proceeds within the forward delay circuit up to the entrance of an n+1th clock into the mirror image control circuit. When the n+1th clock is inputted to the mirror image control circuit, the nth clock is transferred from the forward delay circuit to the backward delay circuit. The nth clock passes through the backward delay circuit substantially in the same time as when it has passed through the forward delay circuit, and is then inputted to the clock driver. As a result, the output of the clock driver supplied with the nth clock is different from an n+2th external clock in phase. That is, the time between the nth clock having passed through the delay monitor and the n+1th clock is measured as the number of stages of delay circuits, and they are further caused to pass through the delay circuits by the number of the stages, whereby an internal clock matched with the n+2th external clock in phase is generated. Accordingly, the SMD is capable of generating an internal clock matched with an external clock in phase in two clock cycles since the commencement of its operation.
The following is known as a reference in which another conventional clock reproducing circuit with no feedback circuit has been described. SMDs are disclosed even in Japanese Patent Application Laid-Open Nos. Hei 10(1998)-126254 and 8(1996)-223031. In addition to these, T. Yamada, et al., 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 112-113, and Japanese Patent Application Laid-Open No. Hei 7(1995)-106956 are known.
In the SMD referred to above, the maximum error in phase synchronization between the external clock and the internal clock is equivalent to a delay time corresponding to one delay stage in each of the forward delay circuit and the backward delay circuit. Therefore, a clock reproducing circuit to which a fine-adjustment or -control circuit is added to minimize such an error, is known. Clock reproducing circuits each using SMD even for fine adjustment or control are disclosed in, for example, J. Han, et al., 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 192-193, and Japanese Patent Application Laid-Open No. Hei 10(1998)-13395.
Further, Japanese Patent Application Laid-Open No. Hei 11(1999)-24785 discloses a circuit wherein lattice or grid-like delay circuits (SQUAD) in which logic gates whose two input terminals are respectively coupled to one another with capacitance, are placed in array form to thereby delay a clock signal, are provided for fine control or adjustment of each delay time, and other delay elements for achieving the enlargement of the delay control or adjustment are inserted in a previous stage, whereby an internal clock synchronism with an external clock can be formed. Its premise technique has been disclosed in Japanese Patent Application Laid-Open No. Hei 8(1996)-78951.